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Dieter Wecker

Prozessorentwurf

Jahr: 2015
ISBN-10: 3110 4029 63

RD1125 SPI Slave Peripheral using Embedded Function Block

Ihr wollt IP-Cores auf einem Lattice System benutzen und habt Fragen bzw. Probleme - dann seht hier nach.

RD1125 SPI Slave Peripheral using Embedded Function Block

Beitragvon Harald » Fr 25. Mai 2012, 14:34

Microprocessors often have a limited number of general purpose I/O (GPIO) ports to reduce pin count and shrink package size. To overcome this limitation, port expanders are often employed to provide I/O expansion capabilities. Most generic GPIO expanders use low pin count serial protocols, such as I2C or SPI, as the interface to the master. They allow designers to save the GPIO ports on the microprocessor for other critical tasks. This design provides a programmable solution for serial expansion of GPIOs. It uses a Serial Peripheral Interface (SPI) bus between the microprocessor and the GPIOs. The design provides additional control and monitoring capabilities for the microprocessor when it does not have sufficient GPIOs to do the job. Apart from the GPIO expander, this design also provides a memory interface to the microprocessor. This memory is accessible via the SPI Interface. The SPI memory command interface is similar to those commonly found in discrete SPI memory devices.
This reference design is intended to provide a familiar and intuitive interface extension to the MachXO2™ Embedded Function Block (EFB). The EFB SPI module supports the major features of SPI bus. Users can take advantage of the MachXO2 hardened SPI port to provide a port expansion or a memory extension. The user is spared from learning operational details of the SPI protocol, the WISHBONE bus or the EFB block. More information you can find on the Lattice web page: http://www.latticesemi.com/products/cpl ... /index.cfm
Reference Designs at Lattice are free of charge !
Harald
 
Beiträge: 11
Registriert: Do 28. Okt 2010, 14:03

Re: RD1125 SPI Slave Peripheral using Embedded Function Bloc

Beitragvon Samhold » Do 22. Nov 2012, 18:31

Harald hat geschrieben:Microprocessors often have a limited number of general purpose I/O (GPIO) ports to reduce pin count and shrink package size. To overcome this limitation, port expanders are often employed to provide I/O expansion capabilities. Most generic GPIO expanders use low pin count serial protocols, such as I2C or SPI, as the interface to the master. They allow designers to save the GPIO ports on the microprocessor for other critical tasks. This design provides a programmable solution for serial expansion of GPIOs. It uses a Serial Peripheral Interface (SPI) bus between the microprocessor and the GPIOs. The design provides additional control and monitoring capabilities for the microprocessor when it does not have sufficient GPIOs to do the job. Apart from the GPIO expander, this design also provides a memory interface to the microprocessor. This memory is accessible via the SPI Interface. The SPI memory command interface is similar to those commonly found in discrete SPI memory devices.
This reference design is intended to provide a familiar and intuitive interface extension to the MachXO2™ Embedded Function Block (EFB). The EFB SPI module supports the major features of SPI bus. Users can take advantage of the MachXO2 hardened SPI port to provide a port expansion or a memory extension. The user is spared from learning operational details of the SPI protocol, the WISHBONE bus or the EFB block. More information you can find on the Lattice web page: http://www.latticesemi.com/products/cpl ... /index.cfm
Reference Designs at Lattice are free of charge !


Nice. I am interested in Lattice products and technique and I will check this out. Thanks for the info!
Samhold
 
Beiträge: 18
Registriert: Mi 3. Okt 2012, 12:21


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